The past few years have seen substantial shifts in how logic content is delivered into electronic systems. The most dramatic of these changes is the sharp reduction of traditional ASIC design starts — ...

Paul Taubman is a senior design engineer for Tality Corp., Cadence Design Systems' services organization. In this article he shows how test engineers should interact with designers in order to ...

In this white paper, we’ll review the many steps of today’s common ASIC/SoC power methodologies and tool flows. We’ll then propose ways you can further optimize your power methodology to more quickly ...

In this paper, the authors present a novel technique for the mapping of set of DSP applications onto architectures targeting an ASIC/Reconfigurable implementation embedded on the same chip. Synthesis ...

It is important to model an SoC well in advance to avoid costly over design or insufficient performance and to create a hardware emulation on which representative end user applications can be run. It ...