EDN

Xilinx releases ISE Design Suite 10.1

Editor”s Note: See also the related “How To” design article: Strategies for minimizing Xilinx implementation tool runtimes. In this article, author Philippe Garrault presents a variety of strategies ...
EDN

Latest Xilinx ISE Design Suite supports plug-and-play ASIC-FPGA design

The guys and gals at Xilinx have just announced the release of version 12.3 of their ISE Design Suite. This release kicks-off the roll-out of Intellectual Property (IP) cores that meet the AMBA 4 AXI4 ...
Design-Reuse

Synopsys Announces FPGA Synthesis Support for Xilinx's Newest ISE Design Suite 13

Designers using Synopsys' Synplify Pro® and Synplify® Premier FPGA synthesis software, in conjunction with Xilinx's latest ISE Design Suite 13, can achieve high design performance for Virtex®-7, ...
Design-Reuse

Xilinx Announces ISE Design Suite 13.4 Further Extending 7 Series FPGA Support and Design Productivity

Latest release includes the New MicroBlaze Micro Controller System, Enhanced Debug with 2D Eye Scan and Partial Reconfiguration Support for Artix-7 and Virtex-7 XT FPGAs SAN JOSE, Calif. -- Jan. 18, ...
New Electronics

Xilinx updates ISE Design Suite to support AMBA 4 AXI4 spec

As the first stage in the introduction of IP cores that meet the AMBA 4 AXI4 specification for interconnecting functional blocks in SoC design, Xilinx has released ISE Design Suite 12.3. "Xilinx is ...
Electronics Weekly

Clock gating is key to improved design flow, says Xilinx

Intelligent clock gating is key to Xilinx’s bid to reduce dynamic block-RAM (BRAM) power consumption in its Virtex-6 FPGA designs. The key to this fourth generation partial reconfiguration design flow ...