Semiconductor Engineering

The PCB Engineer’s Guide To Successful DDR Bus Design

This paper tackles the critical signal integrity concerns encountered when designing, simulating, and analyzing DDR buses. The first section describes DDR bus design challenges that can be ...
Ars Technica

DDR 133 vs 200 Mhz FSB

Would a 200 Mhz FSB be faster (move-more-data) than a double-pumped 133 Mhz DDR bus. The old info that I had (I was corrected as to DDR speed issues in MacAch not long ago) indicated that a double ...
Electronic Design

DDR Bus Simulator to solve BER contour simulation challenge

September 30, 2014. Keysight Technologies today introduced the DDR Bus Simulator—the industry’s first tool to generate accurate Bit-Error-Rate (BER) contours for the JEDEC DDR memory bus specification ...
EDN

Via ships DDR chip set without P4 bus license

TAIPEI, Taiwan — Via Technologies officially launched its double-data-rate SDRAM chip set Wednesday (Aug. 15), despite still being at odds with Intel Corp. over licensing for the Pentium 4 bus.
EDN

Tektronix enhances DDR test and validation portfolio with two new additions

Tektronix today announced enhancements and upgrades to its DDR test and validation portfolio. New interposers being introduced for the Tektronix TLA7000 Series logic analyzers provide engineers with ...
Electronic Design

DDR Bus Termination Regulator from Diodes Incorporated Handles Upgrades to DDR4

Diodes Incorporated has introduced a low-dropout linear regulator capable of generating the bus termination voltages needed by DDR 2, 3, 3L and 4 SDRAM memory systems. Diodes Incorporated has ...
Ars Technica

DDR 133 vs 200 Mhz FSB [copied from Mac Achaia]

Would a 200 Mhz FSB be faster (move-more-data) than a double-pumped 133 Mhz DDR bus. The old info that I had (I was corrected as to DDR speed issues in MacAch not long ago) indicated that a double ...