Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...

Memory test at-speed isn�t easy but can be achieved by balancing test selection, area overhead, and test-time constraints. The semiconductor industry has intensified its focus on yield issues to ...

When semiconductor devices had geometries of 0.18 microns and larger, most defects manifested themselves as static faults. Test strategies based on stuck-at fault-model scan patterns and standard ...

With logic gate counts on microprocessors soaring, chipmakers now face a vexing problem -- how to test a billion-gate chip in a reasonable amount of time. The challenge of testing the so-called ...

General Atomics (GA) announced today that the company is collaborating with the U.S. Department of Energy (DOE) to develop ...

The advent of delivering 10 Gigabit Ethernet connections to the enterprise and data center opens up a myriad of test challenges. Constructing a comprehensive and standards-based test environment is ...