8.2 A logic circuit with active low synchronous reset has two c... | Filo
8.2 A logic circuit with active low synchronous reset has two c... | Filo
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Figure Q2 shows a 74LS163, an integrated circuit 4-bit synchronous binary counter. An active-LOW clear input will synchronously reset the counter. ENT and ENP are two enable inputs. Design a divide-by-48 counter using two cascaded 74LS163 counters, one for a modulus-8 counter and the other for a modulus-6 counter. This counter has an output Y which is HIGH only at the maximum count.D.D. D,DCLR LOAD ENT ENP CLKCTRDIV16TC=15RCO>CQ0QQQFigure Q2
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